今天用modelsim发现include关联的文件编译报语法错误，原来文件名需要写绝对路径，即使这个文件和工程其它文件在一个目录上。
例如只写成 `include "define_file.v" 是不行的，要使用绝对路径，如 `include "F:/110503_Test/rtl/define_file.v"。
详情如下：
QUESTION:
From Xilinx ISE I get the following error:
ERROR:HDLCompilers:26 - "rtl/definitions.v" line 2 expecting 'EOF',
found 'parameter'
When I compile in ModelSim I get the following error:
** Error: D:/rtl/rf_board_top.v(23): Cannot open `include file
"definitions.v".
How to get ModelSim to find the include file (it is in the same
directory as the Verilog modules)?
ANSWER:
I moved the `include after the port definitions and that fixed ISE
problem.
I changed the properties on each .V source file to include the
directory where the include file was located (even though it was the
same directory as the source .v files). This fixed the ModelSim
problem.
重点在最后一段。“更改每一个.V文件的属性，让其包含文件所在的位置（尽管它是跟原.V文件是相同的位置）。这样就解决了modelsim的问题”
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