最近学习FPGA，FPGA为xilinx Vertex V系列，xc5vlx50-1ff1153。软件ISE 10.1。语言采用VHDL语言。以前有Verilog HDL的基础，用Altera的FPGA做过一些东西，不过对现在的系统还是不熟悉，要重新学起。
首先学了学语言，看的是VHDL数字电路设计教程（Ciecuit Design with VHDL），一书，英文电子版我也有的。书很薄，讲的全面精简，而且是基于程序的，很使用。ISE的教程，先看了xilinx的ISE 10.1 Quick Start Tutorial，对ISE的主要设计流程有了了解。下了一本xilinx ise 9.x fpga cpld设计指南的电子书，感觉不错。再就是基于V6的电子工程师创新设计必备宝典系列，很务实的一本书。基础有了就开始着手研究一个DLP的程序了。
    在学习过程中遇到了不少问题，一一记录下来，留下学习的脚印。

1、 实体 entity
Entity，component，component instance 的区别
There is an important distinction between an entity, a component, and a component instance in VHDL.The entity describes a design interface, the component describes the interface of an entity that will be used as an instance (or a sub-block), the component instance is a distinct copy of the component that has been connected to other parts and signals. To compare these with the process of bread board design with off-the-self parts.
Entity，architecture的区别
The entity and architecture is like the data book describing the interface and schematics of how the part works. The component is like the short pin listing that comes with the part to describe how it should be connected. The component instance is the actual part itself, of which you may have many that each operate independently.

在一个项目中entity是必须要有的，一个entity中可以有多个architecture。

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